Spin motor control system for a hard disk assembly

ABSTRACT

A spin motor control system includes a BEMF commutation circuit, a startup circuit and a monitor circuit, each of which operate utilizing digital techniques. The BEMF commutation circuit includes first and second counters that are programmable to accommodate for changing system parameters. The BEMF commutation circuit does not require the incorporation of an external capacitor, is insensitive to leakage current, and provides stable timing characteristics. The startup circuit also includes a counter and is programmable to accommodate for changing system parameters. The startup circuit does not require an external capacitor and provides stable generation of the startup pulses. The monitor circuit includes first and second counters for blanking the BEMF circuitry after commutation. The monitor circuit further includes circuitry for detecting and correcting the direction of rotation of the spin motor. The monitor circuit provides a microprocessor interface to allow for changing motor parameters and environmental conditions, eliminates the requirement of a capacitor, and provides stable timing characteristics.

This application is a continuation-in-part of application Ser. No.07/630,470, filed Dec. 19, 1990, now U.S. Pat. No. 5,258,695.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to motor control systems, and moreparticularly to a spin motor control system for disk drive apparatus.

2. Description of the Relevant Art

Magnetic disk storage systems such as hard disk drive systems and floppydisk drive systems have been and continue to be the predominantmechanisms for providing large volumes of relatively low-cost computeraccessible memory or storage. A typical hard disk drive system includesa number of adjacently positioned disks coated with an appropriatemagnetic material that are mounted for rotation on a common spindle. Thetypical system further includes a set of transducer heads carried inpairs on elongated supports for insertion between adjacent disks whereinthe heads of each pair face in opposite directions to engage oppositesurfaces of the adjacent disks. The transducer heads transform magneticvariations into electric variations when reading data stored on thedisks, and transform electric variations to magnetic variations whenwriting data to be stored on the disks. The support structure is coupledto a positioner motor that typically includes a coil mounted within amagnetic field for linear movement and is typically oriented relative tothe disks to move the heads radially over the disk surfaces to therebyenable the heads to be positioned over any annular track on thesurfaces. During normal operation, the positioner motor, in response tocontrol signals from a host computer, positions the transducer headsradially for recording data signals on, or retrieving data signals from,a pre-selected one of a set of concentric storage tracks on the disks.

A typical hard disk drive system also includes a spin motor operativelyconnected to the spindle for rotating the magnetic disks during dataread and data write operations. An electronic control and drivingcircuit is coupled between the spin motor and the host microprocessorinterface to provide drive signals to the motor windings to therebycontrol the speed and other operating parameters of the spin motor, aswell as to control initial start-up of the spin motor.

FIG. 1 is a schematic view of a portion of a three-phase brushless spinmotor 10 connected to associated control and drive circuitry. For theparticular example illustrated herein, spin motor 10 is a twelve polemotor having nine windings. The nine windings are grouped into threesets, wherein each winding set is selectively driven at a predeterminedphase and is represented by one of phase windings 12, 14, 16. As knownto those skilled in the art, a sequencer 18 and a motor amplifier 20collectively operate to selectively drive the phase windings 12, 14, 16in a manner as explained below to thereby induce rotation of the rotorshaft of motor 10.

Referring next to FIG. 2A in conjunction with FIG. 1, traces 1, 2, and 3illustrate the motor torque generated when a constant current flowsthrough selected pair combinations of phase windings 12, 14, 16 withrespect to motor electrical degrees. Trace 1 shows the motor torquecurve with respect to electrical degrees when transistors 20a and 20fare turned on (20b-20e turned off), resulting in the flow of currentfrom phase A winding 12 to phase C winding 16. Similarly, trace 2 showsthe motor torque curve on the common horizontal axis when transistors20a and 20d are turned on, resulting in the flow of current from phase Awinding 12 to phase B winding 14. Finally, trace 3 shows the motortorque curve when transistors 20d and 20e are turned on, resulting inthe flow of current from phase C winding 16 to phase B winding 14. Theextremum torque points occur 60 electrical degrees apart. For a twelvepole motor, 360 electrical degrees correspond equivalently to 1/6 of amechanical revolution of the rotor.

To spin the rotor in one continuous direction, the motor torque must beeither continuously positive or continuously negative. A continuouslypositive motor torque, for example, can be provided by designing andcontrolling sequencer 18 to turn on selected pairs of the transistors20a-20f in a predetermined and precisely timed sequence to thus resultin an overall torque curve as defined along the extremum segmentsconnecting a1-a7. It should be noted that the curve connecting segmentsa4-a7 results from the flow of current in a reverse direction throughthe respective phase winding pairs. The overall torque curve definedalong the segments a1-a7 results in maximum torque with the leastripple, and thus is considered the result of optimal commutation timing.The predetermined sequence required for turning on the transistors20a-20f as controlled by sequencer 18 is as follows:

Sequence 1: Transistors 20a and 20f turned on - - - Current flows fromphase A winding 12 to phase C winding 16 - - - Generates torque segmenta1 to a2;

Sequence 2: Transistors 20a and 20d turned on - - - Current flows fromphase A winding 12 to phase B winding 14 - - - Generates torque segmenta2 to a3;

Sequence 3: Transistors 20d and 20e turned on - - - Current flows fromphase C winding 16 to phase B winding 14 - - - Generates torque segmenta3-a4;

Sequence 4: Transistors 20b and 20e turned on - - - Current flows fromphase C winding 16 to phase A winding 12 - - - Generates torque segmenta4-a5;

Sequence 5: Transistors 20b and 20c turned on - - - Current flows fromphase B winding 14 to phase A winding 12 - - - Generates torque segmenta5-a6; and

Sequence 6: Transistors 20c and 20f turned on - - - Current flows fromphase B winding 14 to phase C winding 16 - - - Generates torque segmenta6-a7.

The control system for triggering the sequencer 18 typically includes acircuit for generating triggering pulses while the motor is spinning, astartup circuit for generating triggering pulses to initially spinup themotor from a stalled condition, and a monitor circuit for detecting andcorrecting the direction of rotation and for providing a "blanking"signal as will become evident when the following description is fullyappreciated. Each of these circuits is considered separately below.

In early hard disk drive systems, the commutation timing of thebrushless motor as it was spinning was controlled using Hall Effectsensors which were placed within the motor. As disk drives shrunk insize (31/2 and 21/2 inch form factors), space became extremely limitedand thus the Hall sensors were removed from the spin motor to decreaseits size.

In accordance, another method was developed to determine the optimaltiming required for triggering the sequencer circuit to thus commutatethe spin motor. This method involves the phenomenon of backelectromotive force (BEMF). The BEMF signals generated for a three phasemotor when measured with respect to the center tap are shown as signals4, 5 and 6 in FIG. 2B. It is evident that the BEMF signals cross thezero voltage axis when the motor torques are at their extremum values.To provide the least amount of torque ripple, the motor is commutated at30 electrical degrees before and after the extremum torque points. Theseideal motor commutation times are shown both in FIG. 2C and in FIG. 3A.

Analog comparators are connected across each phase winding 12, 14, 16 ofthe motor to determine when each of the BEMF signals is greater thanzero. The output signals generated by these comparators are shown inFIGS. 3B-3D. The comparator signals of FIGS. 3B-3D are logically decodedto generate the tachometer signal as shown in FIG. 3E. Such generationof the tachometer signal is known to those skilled in the art. It isnoted that the optimal motor commutation times are shown to occur at themidpoint of each high and low state of the tachometer signal asrepresented at points X and Y, respectively.

The midpoints X and Y of each high and low state of the tachometersignal are determined in accordance with the circuits of FIGS. 4A and4B. The voltage waveforms generated across the capacitors 22 and 28 ofthe circuits are shown in FIGS. 3F and 3G, respectively. To generate thewaveform of FIG. 3F, capacitor 22 is charged with a constant currentsource 24 during the high period of the tachometer signal and is thendischarged at twice the rate with a constant current sink 26 where thetachometer signal changes states. When the spin motor is running atnominal speed, the capacitor 22 reaches its lowest level at point Ywhich is the desired time to commutate the motor. Capacitor 22 iscombined with additional sensing and triggering circuitry connected tothe sequencer 18 to thereby commutate the motor amplifier 20 to the nextphase.

The capacitor 28 of FIG. 4B is provided to determine the commutationpoints labeled X. This is accomplished by charging the capacitor 28 witha constant current source 27 during the time at which capacitor 22 isbeing discharged, and then holding the voltage charged until thetachometer signal changes to a high state. At this time, the capacitor28 is discharged with constant current sink 29 that has the samemagnitude as but the opposite polarity of current source 27. When thecapacitor 28 reaches its minimum voltage level, sensing and triggeringcircuitry connected thereto senses the minimum voltage condition andthereby causes sequencer 18 and thus the motor amplifier 20 to toggle tothe next phase state of the sequence.

The above-described BEMF technique for determining commutation timingworks well in that when the spin motor is first starting up, thecommutation points are not fixed in time. If the values of capacitors 22and 28 are chosen correctly, the method can be used to commutate themotor even during the initial spinup of the motor. During the initialspinup of the motor, the frequency of the tachometer signal varies. Theupper charge levels of capacitors 22 and 28 is not critical, and thus ifthe period is longer, the capacitors 22 and 28 will simply charge to ahigher level. When the tachometer signal changes states due to azero-crossing of the BEMF signal, the respective capacitor 22, 28 willbe discharged. When the lowest voltage level or some other predeterminedvoltage threshold level is reached, the sensing and triggeringelectronics sequences the motor to the next commutation state.

Although the technique is seemingly ideal in principle, severaldisadvantages are associated therewith. Firstly, several factorsassociated with current sources 24, 27 and with the current sinks 26, 29are critical. Current sources 24, 27 and current sinks 26, 29 must bewell matched. If they are not precisely matched, the commutation pointsare incorrectly determined.

In addition, the absolute values of the current sources 24, 27 and sinks26, 29 must be well controlled from one spindle driver integratedcircuit chip to another. If the absolute values are not well matched,the dynamic range of speed control becomes inconsistent from one unit tothe next.

Furthermore, since the current sources 24, 27 and sinks 26, 29 areusually in the low microamp range, they are subject to various leakagepaths on a printed circuit board. This problem can effect the timeconstant of the respective capacitor 22, 28 being charged and dischargedand thus can cause the motor to be commutated at a non-optimal time.

Several factors associated with capacitors 22, 28 are also critical.Capacitors 22, 28 may change in capacitance value due to temperature andhumidity conditions. This can also be detrimental to the dynamicoperating range of the speed control system.

In addition, the type of dielectric used for the capacitors 22, 28 mustbe considered. Material such as X7R exhibits a piezoelectric effectwhich causes a noise pulse at the end of the respective capacitor 22, 28discharge cycle which can cause the sensing electronics to causecommutation of the motor to the next phase at the wrong time.

Furthermore, the values of capacitors 22, 28 must be relatively large,and thus it becomes impractical to place them within the spindle driverintegrated circuit chip.

Finally, if the timing requirements for commutation of a particularsystem must be modified, the capacitors 22, 28 must typically be changedwhich therefore involves rework of the printed circuit board.

The above description considers the commutation of the spin motor phasewindings 12, 14, 16 during normal operation when the motor is spinning.The commutation of the phase windings 12, 14, 16 is next considered atinitial operation when the spin motor is started from a stalledcondition. When the motor is stalled, there is no generated BEMF signal,and the motor must be spinning at a certain speed in order to generatean adequate BEMF signal to drive the above described sensing electronicsto control commutation.

Thus, from a stalled condition, the motor is typically treated as a stepmotor and is thereby caused to rotate at a constant speed. This speed isdetermined by the parameters of inertia, torque constant, number ofpoles, and current applied.

One known implementation for spinning up the spin motor involves the useof a capacitor 30, a current source 32, a pair of current sinks 34, 36,an electronic switch 38, comparators 40, 42, and a pair of oneshotcircuits 44, 46 as illustrated in the schematic of FIG. 5. Othercomponents described earlier are also included in the schematic and arenumbered similarly. Referring to the schematic in conjunction with thewaveforms of FIGS. 6A-6C, during initial spinup when the motor isspinning too slowly to generate a sufficient BEMF signal, switch 38 isin position 1 and capacitor 30 is thereby charged by current source 32.The voltage charged across capacitor 30 is shown as segment A-B in FIG.6A. When the voltage across capacitor 30 reaches the reference voltageVR1, comparator 40 provides a control signal to a control logic circuit48 that responsively causes switch 38 to move to a position 2. Whenswitch 38 is moved to position 2, current sink 34 is connected todischarge capacitor 30 until a voltage equal to voltage reference VR2 isreached. When comparator 42 senses a voltage less than reference voltageVR2, the control logic toggles switch 38 back to position 1. Thecapacitor 30 voltage thereafter starts to charge again along the segmentC-D. Comparator 42 also generates a positive pulse (when the voltageacross capacitor 30 exceeds reference voltage VR2). The pulse isreceived at oneshot circuit 44 which responsively generates acommutation triggering pulse to the sequencer 18. The sequencer 18controls the phases of the motor amplifier that are active. This processrepeats until the motor gains sufficient speed to start generating theBEMF signal.

When point H is reached, a BEMF commutation pulse is generated. Thispulse triggers oneshot circuit 46 which thereby causes the control logic48 to toggle switch 38 to position 3. Capacitor 30 discharges for agiven period of time, as shown following point H. This discharge time isdetermined by control logic 48. As the number of BEMF pulses generatedincreases, the voltage across capacitor 30 is repetitively discharged bycurrent sink 36 and is discharged below voltage reference VR2. When thisoccurs, the output signals from the two comparators 40, 42 remain lowwithout transitions and thus the sequencer 18 no longer triggered byoneshot circuit 44. The sequencer 18 is thereafter triggered solely bythe BEMF pulse through oneshot circuit 46.

FIG. 6B illustrates the commutation pulses generated by the startuposcillator oneshot circuit 44 and FIG. 6C illustrates the commutationpulses generated by the BEMF oneshot circuit 46. The faster the motorrotates, the more numerous the BEMF pulses. These rapidly occurring BEMFpulses result in the voltage across capacitor 30 to be discharged belowVR2 and thus disables the startup oscillator.

Several disadvantages are associated with this type of startuposcillator. The value of capacitor 30 must be changed if the systemparameters are changed. In addition, capacitor 30 is an external part tothe spindle driver chip and thus requires valuable room in small formfactor disk drives. Finally, current leakage from the capacitor 30 toground can effect the startup commutation frequency. This can cause thespin motor to fail to reach nominal speed in the allotted time. Smalldrives typically require a fast spinup time characteristic, and hence ifthe startup capacitor 30 has excessive leakage, the drive will fail therequirement.

Another method used to start motors involves a variable-time timingcircuit used to step the sequencer. The time characteristics for thetimer is based upon the motor and the load parameters. This techniquemust be very conservative since it is configured in an open looporientation. If the timing characteristics are too aggressive, the motorwill fail to spinup. With conservative timing characteristics, the motorspinup time is relatively long which is a drawback for use in small diskdrives. The conservative timing characteristics are in part required toaccommodate changes in load, motor parameters and environmentalconditions.

Another important aspect to be considered in the design of a spin motorand the associated control circuitry involves a monitor circuit. Themonitor circuit for a brushless DC (BDC) motor serves two functions. Thefirst function is to degate or blankout momentarily the BEMF commutationcircuitry whenever a motor phase winding is turned off. Referring to theschematic of FIG. 7 and the associated waveforms of FIGS. 8A-8C,consider first a current flowing from phase A winding 12 to phase Cwinding 16. This current causes the rotor to rotate from point a1 topoint a2. When point a2 is reached, the sequencer 18 commutates themotor 10 such that current flows from phase A winding 12 to phase Bwinding 14. Phase C winding 16 is the phase winding that is now used tomeasure the BEMF signal since it is the turned-off winding. However,before the BEMF signal can be monitored, the residual current in thewinding 16 due to the prior phase must be allowed to discharge through adiode 60 to a storage capacitor 62. The time required to discharge thephase winding is referred to as blanking time, diode flyback, or reverserecovery time. The BEMF signals generated by each phase winding areshown in FIG. 8B. The noise "glitches" shown in each BEMF signal 4-6result from the residual current discharge explained above and cause thesignals to cross through the zero voltage level, for example, at pointsW and Z. FIGS. 9B, 9C, and 9D are waveforms of the BEMF comparatoroutput signals for each phase winding and indicate when each phasewinding has a positive BEMF signal. The noise glitches of the BEMFsignals 4-6 cause corresponding glitches (labelled as points N on thetraces) in the comparator output signals which thus interfere with thegenerated tachometer signal. For this reason, a delay time shown assegment D is required following a commutation triggering pulse beforethe BEMF signal is processed. Thus, the first task of the monitorcircuit is to provide the delay after a commutation pulse.

The second function of the monitor circuit is to detect if the motor isrotating in the proper direction. Referring back to FIGS. 8A and 8B, ifphase A to C is energized at point a1 and the motor is rotated to pointa2, the BEMF signal 6 of phase C winding 16 should have a negativepolarity (segment E) immediately following the commutation trigger pulseand delay time (segment D) described above. If the signal has a positivepolarity, the motor is spinning in the wrong direction, and thereforethe motor should be commutated to the next phase. This allows the motorto catch up and start generating torque of the proper polarity.

The two functions of the monitor circuit have traditionally beenaccomplished using current sources and comparators. FIG. 10 shows aschematic of a monitor circuit for providing a blanking delay and forproviding false BEMF detection and direction correction, and FIGS.11A-11E show the waveforms generated. One of three actions trigger thecircuit: a BEMF commutation pulse provided at line 80, a startuposcillator commutation pulse provided at line 81, or the internallygenerated monitor false polarity correction pulse provided at line 82. Atrigger pulse received at any of lines 80, 81, 82 is provided to controlblock 84 through OR gate 85. When a trigger pulse is received, controlblock 84 causes switch 86 to close and thereby causes charging ofcapacitor 87 with current source 83. In addition, control block 84causes flip-flop 88 to set to a high state. The time period from theoccurrence of the trigger pulse until capacitor 87 charges to voltagereference VR3 is the delay time (segment D) as shown in FIGS. 11A and11B. When the delay pulse of FIG. 11B is high, the BEMF comparators aredegated and are thus not allowed to change states. When the voltageacross capacitor 87 reaches voltage reference VR3, comparator 93 enablesAND gate 89. Comparator 90 monitors (at line 99) whether the polarity ofthe BEMF signal from phase C winding 16 is negative while AND gate 89 isactive (during the time period when the pulse as shown in the waveformof FIG. 11C is high). If the BEMF is negative, OR gate 91 provides asignal to control block 94 which thereby causes capacitor 87 to bedischarged by closing switch 95 (FIG. 11D). OR gate 91 also provides asignal that causes flip-flop 88 to be reset to a low state.

If the BEMF signal from phase C winding 16 is positive, then the outputof AND gate 89 remains inactive. Capacitor 87 thus charges to voltagereference VR4 at point F (FIG. 11E) and thereby generates a falsepolarity commutation pulse as shown in FIG. 11F by means of comparator96. The false polarity commutation FPC pulse signal is received atcontrol block 94 through OR gate 91 that accordingly dischargescapacitor 87. The FPC pulse signal is also received at control block 84through OR gate 85 such that when capacitor 87 has been discharged, itwill be recharged by current source 83 and the process repeated. The FPCpulse signal is finally provided to the sequencer so that the motor iscommutated to the next state.

The blanking and direction control circuit described above hasdisadvantages in that an external capacitor 87 is required. In addition,the circuit does not optimally accommodate for changing motor parametersand environmental conditions.

Numerous other magnetic disk storage systems and components thereofrelating particularly to spin motor control have been disclosed. Ofgeneral interest in the field of spin motor control are U.S. Pat. No.4,933,785 to Morehouse et al., issued Jun. 12, 1990; U.S. Pat. No.4,568,988 to McGinlay et al., issued Feb. 4, 1986; U.S. Pat. No.4,638,383 to McGinlay et al., issued Jan. 20, 1987; U.S. Pat. No.4,371,903 to Lewis, issued Feb. 1, 1983; U.S. Pat. No. 4,737,867 toIshikawa et al., issued Apr. 12, 1988; and the publication "Quantum LowPower Products: Go Drive-21/2-inch Hard Disk Drives-ProDrive GemSeries-31/2-inch Small Frame Devices-Technical Highlights", September1990.

SUMMARY OF THE INVENTION

A spin motor control system according to the present invention includesa BEMF commutation circuit, a startup circuit, and a monitor circuit,each of which operate without the above-described disadvantages. TheBEMF commutation circuit of the present invention is programmable toaccommodate for changing system parameters and does not require theincorporation of an external capacitor. In addition, the BEMFcommutation circuit is insensitive to leakage currents and has stabletiming characteristics. The startup circuit of the present invention isalso programmable to accommodate for changing system parameters, doesnot require an external capacitor, and provides stable generation of thestartup pulses. Finally, the monitor circuit of the present invention isprogrammable, does not require an external capacitor, and providesstable timing characteristics.

These and other advantages are provided with the present invention, inaccordance with which a control circuit for a spin motor comprises aback EMF sensing circuit connectable to at least one winding of the spinmotor for providing a first signal derived from the back EMF induced insaid winding. In addition, a first counter is coupled to the back EMFsensing circuit.

The control circuit may further include a second counter coupled to theback EMF circuit, and first and second zero detectors coupled to thefirst and second counters, respectively. A microprocessor interface isprovided to allow programming of the first and second counters.

In accordance with another aspect of the invention, a startup controlcircuit for a spin motor comprises a counter for counting in apredetermined startup sequence when the spin motor is stalled andfurther comprises a startup pulse generating means coupled to thecounter for generating a startup pulse depending upon a predeterminedcondition of the counter. In addition, the startup control circuitcomprises a BEMF processing means coupled to the counter for causing thecounter to count in a sequence other than the predetermined startupcounting sequence when a BEMF commutation pulse is received.

In accordance with a final aspect of the invention, a monitor circuitfor a spinup motor comprises a first counter for controlling a delayperiod signal for blanking a BEMF pulse and means for receiving a BEMFsignal coupled to the first counter. The monitor circuit furthercomprises means coupled to the first counter for providing the pulse toan output terminal depending upon the delay period signal.

The invention will be more readily understood by reference to thedrawings and the detailed description. As will be appreciated by oneskilled in the art, the invention is applicable to motor control systemsin general, and is not limited to the specific embodiment disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a spin motor commutation sequencingcircuit.

FIG. 2A is a set of traces illustrating motor torque with respect tomotor electrical degrees.

FIG. 2B is a set of waveforms illustrating the BEMF signals generated ineach phase winding of a spin motor with respect to motor electricaldegrees.

FIGS. 2C and 3A are timing diagrams illustrating the ideal commutationtimes and active phase windings with respect to motor electricaldegrees.

FIGS. 3B-3D are a set of waveforms illustrating output signals from BEMFsignal comparators.

FIG. 3E is a waveform of a tachometer signal.

FIGS. 3F and 3G are waveforms illustrating the voltage levels across aset of capacitors.

FIGS. 4A and 4B are schematic diagrams of circuits for determiningoptimal commutation times.

FIG. 5 is a block diagram of a spinup oscillator circuit.

FIGS. 6A-6C are a set of waveforms associated with the circuit of FIG.5.

FIG. 7 is a schematic diagram illustrating residual current discharge inthe phase C winding.

FIG. 8A is a set of traces illustrating motor torque with respect tomotor electrical degrees.

FIG. 8B is a set of waveforms illustrating the BEMF signals that havedischarge current glitches generated in each phase winding of the spinmotor.

FIGS. 8C and 9A are timing diagrams illustrating ideal commutationtimes.

FIGS. 9B-9D are a set of waveforms illustrating the effect of glitcheson the BEMF comparator output signals.

FIG. 10 is a block diagram of a monitor circuit.

FIGS. 11A-11F are a set of waveforms associated with the monitorcircuit.

FIG. 12 is a block diagram of a hard disk drive system.

FIG. 13 is a block diagram of a spin control and drive portion of thedisk drive system.

FIG. 14 is a schematic diagram of a commutation circuit for a spinmotor.

FIG. 15 is a block diagram of a BEMF commutation control circuit inaccordance with the invention.

FIG. 16A is a waveform illustrating a tachometer signal.

FIGS. 16B and 16C are graphs illustrating the value of counters withinthe BEMF commutation control circuit.

FIG. 17 is a block diagram of a startup circuit in accordance with theinvention.

FIGS. 18A-18J are a set of waveforms illustrating operation of thestart-up circuit.

FIG. 19 is a block diagram of a monitor circuit in accordance with theinvention.

FIGS. 20A-20K are a set of waveforms illustrating operation of themonitor circuit.

FIG. 21 is a schematic diagram of a preferred embodiment of the BEMFcommutation circuit.

FIGS. 22A-22P are a set of waveforms illustrating operation of the BEMFcommutation circuit.

FIG. 23 is a schematic diagram of a preferred embodiment of the start-upcircuit.

FIGS. 24A-24N are a set of waveforms illustrating operation of thestart-up circuit.

FIG. 25 is a schematic diagram of a preferred embodiment of the monitorcircuit.

FIGS. 26A-26L are a set of waveforms illustrating operation of themonitor circuit.

FIG. 27 is a block diagram of the control loop for the spindle motor.

FIG. 28 is a schematic diagram of a portion of the control loop.

FIGS. 29A-29N and 30A-30N are a set of waveforms illustrating operationof the control loop.

FIGS. 31 and 32 are a set of waveforms illustrating the bus states toprogram a counter within the control loop.

DETAILED DESCRIPTION OF THE INVENTION

The following includes a detailed description of the best presentlycontemplated mode for carrying out the invention. The description isintended to be merely illustrative of the invention and should not betaken in a limiting sense.

Referring first to FIG. 12, a block diagram of a hard disk drive systemis shown to which the present invention is adapted. The block diagramincludes a microcontroller 200, a gate array 202, a ROM block 204, anactuator 206, an actuator driver block 208, and a formatter/controllerblock 210. The diagram further includes an interface connector 212, aRAM buffer 214, a read/write combo block 216, a R/W preamp 218, a motorand transducer assembly 220, and a spin control and drivers block 222.The components and operation of the hard disk drive system shown aremore completely described in the co-pending and commonly assigned U.S.patent application Ser. No. 07/629,948 of Morehouse et al., filed onDec. 19, 1990 and entitled "Miniature Hard Disk Drive for PortableComputers", which is incorporated herein by reference in its entirety.

Referring next to FIG. 13, a block diagram is shown of the spin controland drivers block 222. The diagram includes a serial port 230, afrequency locked loop circuit 240, a current control circuit 245, a BEMFdetector 250, a startup oscillator 260, a monitor circuit 270, asequencer 280, and a power drivers block 290.

Serial port 230 receives serial clock signals, serial data signals, andchip select signals at input lines 231-233, respectively. Serial port230 is coupled to BEMF detector 250 through a signal bus 234, to startuposcillator 260 through a signal bus 235, to monitor circuit 270 througha signal bus 236, and to frequency locked loop circuit 240 through asignal bus 237. Serial port 230 accommodates for the programming ofcomponents within frequency locked loop circuit 240, BEMF detector 250,startup oscillator 260, and monitor 270, as will become more evidentbelow.

Frequency locked loop circuit 270 is provided to control the speed ofthe spin motor, and includes an input line for receiving a feedbackfrequency signal from gate array 202, and an input line for receiving afeedback frequency signal from BEMF detector 250. A third input line isfurther provided for receiving a reference frequency signal from aninternal timer of gate array 202. Frequency locked loop circuit 240includes an internal counter that is driven by the reference frequencysignal. The counter value is compared to one of the feedback signals(from either gate array 202 or BEMF detector 250) to thereby provide anoutput signal to current control block 245 for precisely controlling thecurrent supplied to the spin motor.

FIG. 14 shows a schematic diagram of a portion of the power driversblock 290. The circuit of FIG. 14 is described more completely inco-pending and commonly assigned U.S. patent application Ser. No.07/630,110 of Morehouse et al. filed on Dec. 19, 1990 and entitled "SpinMotor For a Hard Disk Assembly", which is incorporated herein byreference in its entirety. As it pertains to the present invention, itis important to note that a BEMF voltage is generated across each motorphase, and that this BEMF voltage is processed to generate a tachometersignal as described earlier. The capacitor C1 voltage that is generatedby the BEMF voltage of L1-L6 is also used to unload the transducer headsas described in the co-pending applications. To generate the tachometersignal, only the portions L2, L4 and L6 of the motor are used.

Referring next to FIG. 15, a block diagram of a BEMF commutation circuitprimarily within the BEMF detector 250 is shown. The components of theBEMF commutation circuit include a microprocessor interface 100, twoup/down counters 102, 104, control logic circuits 106, 107, 108, 114,and frequency sources 112 and 113 for supplying signal sources (F1 andF2). The circuit further includes zero detectors 109, 110, AND gates122, 123, OR gates 124, 128, and inverter gates 131, 132.

During operation, comparator and decoding circuitry as describedpreviously is used to generate the tachometer signal of FIG. 3E. Thetachometer signal is provided to line 135 and is thereby received by theup/down control pin of counter 102, by logic circuit 114, and by gates122, 131 and 132.

When the motor is running at nominal speed, counter 102 counts up whenthe tachometer signal is in a high state. Signal F1 from frequencysource 112 is used to clock counter 102. When the tachometer signalchanges to a low state, the counter clock changes to signal F2 fromfrequency source 113 by way of logic circuit 106 and gates 122, 123, 124and 131. Frequency source 113 generates a signal F2 that is twice thefrequency of signal F1. In addition, counter 102 is controlled by thetachometer signal at the U/D terminal to count down. Referring to FIGS.16A and 16B, when counter 102 reaches a count value of zero as detectedby zero detector 110, the tachometer signal is at point Y, which is theoptimal time at which to commutate the motor. Logic circuit 114 holdscounter 102 in a reset state until the tachometer signal goes to a highstate. Logic circuit 114 also generates a BEMF commutation pulse whencounter 102 reaches a count value of zero. This commutation pulse isprovided to the motor sequencer 280 (FIG. 13) through OR gate 128 (FIG.15).

While counter 102 is counting down, counter 104 is counting up withsignal F1 as its clock source. The clock to counter 104 is disabled bylogic circuit 107 when counter 102 reaches a count value of zero. Whenthe tachometer signal changes to a high state, counter 104 is controlledat the U/D terminal to count down (with signal F1 as the source). When acount value of zero is reached, the tachometer signal is at point Xwhich is also the optimal time at which to commutate the motor.Accordingly, logic circuit 108 issues a BEMF pulse on line 126 which iscoupled to the motor sequencer through OR gate 128.

The operation of the BEMF commutation circuit also accommodates for thecommutation of the motor during initial spinup. When the motor is firstturning at startup, the period of the tachometer signal is much longerand counters 102, 104 count to a larger value. Since a much larger countvalue is reached in each counter, it also takes the respective countersmuch longer to count down to zero. Thus, the circuit is self-adjustingcorrecting and commutates the motor at the optimal time regardless ofthe period of the tachometer signal.

A potential problem could exist, however, if the motor is runningextremely slow. For such a case, the tachometer period is very long andcounters 102, 104 may not be sufficiently large to avoid an overflowcondition. This would cause the respective counter 102, 104 to have amuch lower value when the tachometer signal changed state. The wrongcount value would then cause the motor to be commutated at the wrongtime.

The circuit in accordance with the present invention can avoid thisproblem in one of several ways. The circuit can be designed by makingcounters 102, 104 large enough so that overflow conditions can neveroccur. Alternatively, the frequency of signal F1 and of signal F2 can beprogrammed to a lower frequency during startup so that the counters donot count up/down so quickly and thus not overflow. This can be achievedby providing programmable frequency sources 112 and 113 that arecontrollable by the microprocessor.

There are several other advantages provided by the above-describedcommutation control circuit as shown in FIG. 15. By using frequencysources and/or counters that are programmable, motors with widelyvarying parameters can be used without physically changing componentssuch as capacitors. Operating parameters of the spin motor can thus bechanged at the command of the microprocessor, and therefore, if a systemparameter is changed such as substituting disk drives, themicroprocessor can automatically change the operating parameters of thespin motor.

In addition, the requirement for external capacitors is eliminated.Thus, the entire control circuit can be fabricated on a singleintegrated circuit chip to thereby minimize space requirements.

Furthermore, the control circuit is insensitive to leakage currents andcritical timing is not effected by temperature, humidity, and otherenvironmental effects.

Finally, the critical timing is essentially identical from one spindledriver chip to the next, and does not depend upon identical matching ofanalog current sinks and sources.

Referring next to FIG. 17, a block diagram is shown of a startuposcillator circuit 260 that allows the spin motor to be spunup from astalled condition. When the BEMF signal generated by the motor is ofsufficient amplitude, the startup-pulse generating circuitry isdisabled. When disabled, the BEMF signal received at line 116 (from line130 of FIG. 15) is used to commutate the motor amplifier.

The circuit includes a microprocessor interface 140, a frequency clock142, a registers and counter block 144, oneshot circuits 146, 148, andlogic block 150. The circuit further includes a zero count detector 152,a maximum count detector 154, a counter 156, AND gates 158, 160, 162,164, and OR gates 166, 168. The circuit finally includes a sequencer170, a motor amplifier 172, and a spin motor 174.

Sequencer 170, motor amplifier 172, and spin motor 174 operate inaccordance with the above related description. Therefore, the specificsof their operation are not explained again below.

FIGS. 18A-18J show waveforms and signals associated with the startuposcillator. FIG. 18A represents the count value of counter 156 withrespect to motor electrical degrees. FIG. 18B shows the generatedstartup pulses from maximum count detector 154 and FIG. 18C shows BEMFcommutation pulses received at line 116. FIGS. 18D and 18E show outputsignals from AND gates 158 and 160, respectively, and FIG. 18F shows thecontrol signal applied to the U/D terminal of counter 156. FIG. 18Gshows the occurrence of a zero value detected by zero count detector152, and FIG. 18H shows the occurrence of a maximum value detected bymaximum count detector 154. Finally, FIGS. 18I and 18J show outputsignals from gates 164 and 162, respectively.

At initial operation of the disk drive unit, the spin motor isstationary. It is assumed herein that the desired direction of rotationof the spin motor is clockwise. The microprocessor, through theinterface 140, programs the frequency of signals F1 and F2 provided fromblock 144. In addition, the microprocessor further initializes counter156 to zero, sets the oneshot pulse duration times, and sets count valuein the maximum count detector 154. Signal F1 is gated through gates 158,164, 166 to the clock input of counter 156. Accordingly, counter 156starts to count up as shown in FIG. 18A. Counter 156 increases in valueuntil it reaches the maximum count value, which is represented as pointB. At this time, the maximum count detector 154 generates a startuppulse to sequencer 170 through OR gate 168 to commutate amplifier 172.The resulting startup pulse is shown in FIG. 18B. The motor accordinglyswitches to the next phase and logic block 150 simultaneously resetscounter 156 to zero. This sequence continues in the absence of any BEMFgenerated commutation pulses.

The time period represented from point A to point C is set in accordancewith the motor parameters to cause the motor to rotate to the nextcommutation point with each startup oscillator pulse. It should be notedthat the oscillations due to the motor movements should be allowed tosettle down before the next startup pulse is delivered. In addition, theproper setting of the time period A-C is important since if the pulsearrives too soon, the motor may rotate counter-clockwise, whereas if thepulse arrives too late, the motor may not rotate fast enough to generatea BEMF signal.

When point F is reached, the motor is rotating sufficiently fast that aBEMF commutation pulse is generated as shown in FIG. 18C. This pulse isreceived by oneshot circuit 148 that accordingly steps the sequencer tocommutate the motor and amplifier. In addition, oneshot circuit 146 isalso triggered. When oneshot circuit 146 is triggered, counter 156counts down and signal F2 becomes the counter clock. Counter 156 countsdown for the duration of the time programmed in for oneshot circuit 146.This time is shown as the period from point F to point G. After oneshotcircuit 146 times out, counter 156 continues to count up toward point H.Normal operation continues until point J is reached. At this timeanother BEMF pulse is generated and counter 156 is again controlled tocount down. However, during this time, more BEMF pulses are providedfrom the circuit of FIG. 15, thus preventing counter 156 from reachingthe maximum count value. Eventually, counter 156 is driven to a count ofzero. By this time, BEMF pulses are generated fast enough such thatoneshot circuit 146 is continuously triggered. Since the counter 156value is zero, no startup pulses are generated. Thus the startupcircuitry is disabled and the motor 174 and amplifier 172 are commutatedentirely by the BEMF pulses.

As a result of the startup oscillation circuit described above inaccordance with the invention, the frequency of the spinup pulses isprogrammable to accommodate motors with varying parameters and changingenvironmental conditions. Furthermore, the entire circuit can befabricated on a single integrated circuit chip since no externalcapacitor is required. Thus, space requirements are minimized. Finally,variations in the spinup pulses due to capacitance instability and boardleakage are eliminated.

A monitor circuit for blanking out the BEMF commutation circuitry andfor detecting proper spin direction is finally considered. Referring tothe schematic diagram of FIG. 19, a monitor circuit is shown inaccordance with a further aspect of the invention. The monitor circuitincludes counters 180, 182, decode logic circuits 184, 186, and amicroprocessor interface 120 that allows the counters 180, 182 anddecode logic circuits 184, 186 to be programmed differently asconditions or parameters are changed. The monitor circuit furtherincludes a comparator 190 for testing the polarity of the BEMF signal, aflip-flop 192, AND gates 194, 196, 198, OR gates 200, 202, and invertergates 204, 206.

Referring to FIGS. 20A-20K in conjunction with the circuit schematic,initially the microprocessor programs the count length of counter 180and the decode value of decode logic 184 for providing an output signalat the terminal count 1 (TC1) line. This sets the delay period timeduring which the pulse shown in FIG. 20D is asserted. During this timeperiod, the BEMF comparators are degated so that the noise glitches willnot affect their output signals. Counter 182 and the decode value fordecode logic 186 for providing an output signal at the terminal count 2(TC2) line are programmed to set the duration of time as shown in FIG.20E during which the polarity of the BEMF signal is checked after thedelay period.

The circuit is activated through OR gate 200 when either a BEMFcommutation pulse, a startup oscillator pulse, or a TC2 pulse togglesflip-flop 192 to a high state. The output signal from flip-flop 192 isshown in FIG. 20B. When the output signal of flip-flop 192 goes high,AND gate 194 then generates a clock signal as shown in FIG. 20H tocounter 180 and the counter 180 begins counting up as shown in FIG. 20C.When the terminal count 1 (TC1) value is reached AND gate 194 isdisabled and AND gates 196 and 198 are enabled. Thus, counter 182 startsto count up as shown in FIG. 20F in accordance with the clock signalfrom the output line of AND gate 196.

If the motor is not spinning in the correct direction, the BEMF signalfrom Phase C will be positive and thus the output signal of comparator190 will be low, thus allowing counter 182 to reach the terminal count 2(TC2) value in accordance with the clock signal (AND gate 196 outputsignal) of FIG. 20I. When TC2 is reached, flip-flop 192 and counter 182are reset and a pulse as shown in FIG. 20G is issued to the sequencer toadvance the motor amplifier to the next phase. Since the terminalcircuit 2 (TC2) signal is input to OR gate 200, the cycle is repeated.

If the BEMF signal is negative, the output signal of comparator 190 andAND gate 198 is high and thus counter 182 is reset by the output signalof OR gate 202. An example of the counter 182 value during this resetoperation is illustrated in the waveform of FIG. 20J. Note that theclock signal from AND gate 196 as shown in FIG. 20K for this case hasfewer repetitions. Since the motor is spinning in the correct direction,no pulse is issued to the sequencer by means of a TC2 pulse since theterminal count 2 value is not reached. The output signal from OR gate202 causes flip-flop 192 to be reset and the circuit waits for the nextpulse input to OR gate 200.

It is noted that only one comparator 190 is shown in the circuit of FIG.19. Comparator 190 monitors the phase C voltage. Two other comparatorsare similarly connected in the circuit to monitor the voltage signals ofphase A and B.

The monitor circuit described in accordance with the invention providesseveral advantages. Since a microprocessor interface and a serial portare provided, the operating parameters of the circuit can beprogrammably modified to accommodate changing motor parameters andenvironmental conditions. In addition, no external capacitor isrequired, thus minimizing space requirements. Finally, timing variationsdue to variances in capacitance values and due to board leakage currentsare eliminated.

Referring next to FIGS. 21-26, preferred embodiments of the BEMFcommutation circuit, the start-up circuit, and the monitor circuit areshown. Referring first to FIG. 21, the BEMF commutation circuit is showncomprising counters 301-304 which in this embodiment are type 74HC191integrated circuits. The circuit further comprises octal bustransceivers 306 and 307 which in this embodiment are type 74HC245integrated circuits. The circuit additionally comprises latch circuit309 which in this embodiment is a type 74HC374 integrated circuit.

The operation of the commutation circuit is next considered withreference to the timing diagrams of FIGS. 22A-22P. When the TACH SIGNALline 310 changes state, a positive going pulse is generated on the TACHINTERRUPT line 311 which is sent to the microprocessor (not shown). Themicroprocessor then tests the TACH SIGNAL line 310 to determine if theTACH SIGNAL is high or low.

If the TACH SIGNAL is high, counters 301-304 are disabled by a lowsignal on the G inputs of counters 301 and 303. This low signal isgenerated from octal flip flop 309 which is enabled by the ADDR STROBE2. The address strobes are used to write information from the data bus.Similarly, the D/U terminals of counters 301 and 302 are then set highto count down, and the D/U terminals of counters 303 and 304 are set lowto count up. ADDR STROBE 1 enables the count value of counters 301 and302 to be read by the microprocessor data bus by way of the octal bustransceiver 306 which reads the contents of counters 301 and 302 throughCNTR BUS 1. ADDR STROBE 3 then allows the counters 301 and 302 to beloaded with a count value that has been placed on the microprocessordata bus which can be, for example, one half the previously read countvalue. In a similar fashion, ADDR STROBE 5 allows counters 303 and 304to be set to all zeroes by data contained on the data bus 313. Counters301-304 are then enabled and begin to count the 100 KHz clock up anddown respectively. When counter 302 has counted to zero, a signal isplaced on the "0" INTERRUPT BUS 1 to notify the microprocessor whichthen commutates the motor signal. This completes the first part of thecycle.

After the next TACH INTERRUPT signal, the polarity of the signal on theTACH signal line 310 will be low. Counters 301-304 are disabled by a lowsignal on the G input of counters 301 and 303 from octal flip flop 309data bus register. Similarly, the D/U counters 303 and 304 are then sethigh to count down, and the D/U terminals of counters 301 and 302 areset low to count up. ADDR STROBE 4 allows the count value of counters303 and 304 to be read by the microprocessor data bus by way of octalbus transceiver 307 which provides the contents of counters 303 and 304through the CNTR BUS 2. ADDR STROBE 5 then enables counters 303 and 304to be loaded with a count value that has been placed on themicroprocessor data bus which can be, for example, one-half of thepreviously read count value. In a similar fashion, ADDR STROBE 3 allowscounters 303 and 304 to be set to all zeroes by data on the data bus313. Counters 301-304 are then enabled and begin to count the 100 KHzclock down and up respectively. When counter 304 has counted to zero, asignal is placed on the "0" INTERRUPT BUS 2 to notify the microprocessorwhich then commutates the motor signal, thereby completing the cycle.

FIG. 23 illustrates a start-up circuit in accordance with a preferredembodiment of the invention. The start-up circuit shown operates inaccordance with the principles explained above in conjunction with FIG.17. The start-up circuit includes octal flip flops 325 and 326 which inthis embodiment are type 74HC374 integrated circuits. The circuitfurther includes counters 328-330 which are type 74HC191 integratedcircuits, and precision pulse generator circuits 332 and 333 which areimplemented using type 74HC193 integrated counter circuits. Stillfurther, the circuit also includes maximum count detector 335 and zerocount detector 336 which are type 74HC688 integrated circuits. Thecircuit finally includes flip flop 340, NOR gates 342-345, inverters347-348, and NAND gate 349. It is noted that precision pulse generatorcircuits 332 and 333 generate a single pulse at the carry-out lines ofthe integrated circuits and that capacitive timing is not required.FIGS. 24A-24N are timing diagrams associated with the start-up circuitof FIG. 23. The operation of the circuit is evident in accordance withthe principles explained above in conjunction with FIG. 17.

Referring next to FIG. 25, a monitor circuit in accordance with apreferred embodiment of the invention is shown. The monitor circuitshown operates in accordance with the principles explained above inconjunction with FIG. 19. The monitor circuit includes counters 355-358which in this implementation are type 74HC193 integrated circuits. Thecircuit further includes latch circuits 360 and 361 which are type74HC374 integrated circuits, and flip flops 363 and 364 which are type74HC74 integrated circuits. The circuit finally includes NAND gates366-368, AND gate 369, OR gate 370, and comparator 371. FIGS. 26A-26Lshow timing diagrams associated with the monitor circuit of FIG. 25. Theoperation of the monitor circuit is evident in accordance with theprinciples explained above in conjunction with FIG. 19.

Referring finally to FIGS. 27, 28, 29A-29N, 30A-30N, 31 and 32, thecontrol loop for the spindle motor is considered. These figuresillustrate the acceleration phase and steady state motor control loop.Speed control signals are generated by either motor BEMF TACH pulsesfrom the spin motor electronics block 521 or by sector pulses that comefrom the read channel via a gate array block 522. The tach signal sourceis selected by the microprocessor (not shown) that controls switch 501by way of control line 502.

During the motor acceleration phase (FIGS. 29A-29N), switch 501 ispositioned to select the motor BEMF TACH derived signal at line 505 andto provide the signal on line 504. In one implementation, the signalprovided from switch 501 may be 18 pulses per revolution when generatedfrom the motor BEMF TACH pulses at line 505 (925 microseconds at 3600RPM) or 72 pulses per revolution when generated from the sector signalat line 506 (231.47 microseconds at 3600 RPM). Switch 510 is alsopositioned in response to the microprocessor to pass the output signalof the charge pump 511 through filter 512. The signal on line 504 ispassed to the summing circuit 515 where it is compared with referenceclock signal REF1 or with reference clock signal REF2. REF1 is a clockreference of 925 microseconds and is used when the TACH signal isselected as the feedback signal. REF2 is a clock reference of 231.47microseconds and is used when the sector signal is selected as thefeedback signal. Switch 523 is used to select either the REF1 signal orthe REF2 signal. The REF1 and REF2 signals are coupled to summingcircuit 515 through switch 523 and line 524. The output of the summingcircuit 515 is provided to speed discriminator logic block 516 whichprovides output signals to charge pump 511. This circuitry isillustrated in more detail in FIG. 28. Timing diagrams for the circuitare shown in FIGS. 29A-29N and 30A-30N.

Depending on which signal source is chosen through switch 501, aprecision timing pulse is generated to determine the desired controlspeed of the motor. The pulse must match the desired count period asillustrated in FIGS. 29A-29N and 30A-30N. Referring to FIG. 28, this canbe accomplished by loading the dual-timer 601 (type 8254 integratedcircuit) with the appropriate count value by means of the microprocessordata bus. FIGS. 31 and 32 illustrate the bus states to program counter601 during the operation described herein.

It is noted that the crystal controlled clock 606 provides a frequencyreference. Another method to provide more flexibility in the timingperiods, the frequency of crystal controlled counter 605 (type 74HC191integrated circuit) can be lowered by the microprocessor through thedata bus. Thus, the 10 MHz clock 606 can be lowered by a factor of 2-16by counter 605 to thus give counter 601 greater dynamic range.

The summing circuit 515 then analyzes each period by means of precisionpulses generated in an alternating fashion by programmable counterscontained within dual-timer 601. As shown in FIG. 28, the source fortachometer pulses is selected by multiplexer 610 (type 74HC157integrated circuit) and placed at the CLK input of flip flop 613 whichallows the tach pulses to alternately trigger each timer and alsogenerates the tach timing pulse at Q and -Q (FIGS. 29F and 29G). Theprocess repeats when the next tach pulse occurs.

The timer 0 and timer 1 speed control logic elements (AND gates 611, 612and AND gates 614, 615) act as a digital time domain summing circuit,comparing the tachometer signals with the previously mentioned precisiontiming pulses (FIGS. 29H-29K). Depending on the arrival time, an earlyor late pulse is generated by the Slow or Fast OR gates 620 and 621whose duration is therefore proportional to the speed error (FIGS. 29Land 29M). These pulses serve to pulse width modulate the positive ornegative current generators (transistors 625 and 626) which in turncharge or discharge capacitors in the selected filter which results inan integrated voltage representing the speed error (FIG. 29N). Thefilters are generally designed to allow a 35 to 45 degree phase marginin the open loop response, dependent on the tach signal sampledbandwidth. The resultant error voltage is placed at the input to atransconductance amplifier 525 which produces a motor currentproportional to the error voltage, thus controlling the motor torque andacceleration as is well known.

When the microprocessor determines that the spin motor is within 1/2% ofthe target speed. Sector pulses are then generated by the read channeland gate array, and switch 501 is positioned to select the sector pulsesat line 506 as the new tach signal. At the same time, filter 513 isselected by switch 510 and all switches relating to the commutationpulse operation are opened. At the same time, the dual-timer pulsegenerator 601 is reconfigured as mentioned above to produce timingpulses of the desired period as is illustrated in FIG. 30A-30N.Thereafter, the servo loop acts as described above but at a higher gainbandwidth product because of the increased tachometer sampling rate.

It is noted that the system using dual timers is able to evaluate everytach pulse and therefore average out errors caused by pulse pairingespecially during back emf commutation. Therefore, locking to anincorrect speed is prevented when pulse pairing is present withoutdiminishing the servo bandwidth.

Numerous modifications and variations will become apparent to thoseskilled in the art once the above disclosure is fully appreciated. It isto be understood that the above detailed description of the preferredembodiment is intended to be merely illustrative of the spirit and scopeof the invention and should not be taken in a limiting sense. The scopeof the claimed invention is better defined with reference to thefollowing claims.

We claim:
 1. A control circuit for a spin motor having a plurality ofwindings, said control circuit comprising:a back EMF sensing circuitconnectable to at least one winding of said spin motor wherein said backEMF sensing circuit in response to a back EMF induced in said at leastone winding generates a back EMF output signal; a first counter circuithaving an input line coupled to said back EMF sensing circuit and anoutput line coupled to a spin motor sequencer circuit wherein said firstcounter circuit generates a signal on said output line that is used tocommutate a phase of said spin motor; a second counter circuit having aninput line coupled to said back EMF sensing circuit and an output linecoupled to said spin motor sequencer circuit wherein said second countercircuit generates a signal on said output line that is used to commutatesaid phase of said spin motor; and a microprocessor interface coupled tosaid first and second counter circuit, for programming a first countvalue in said first counter circuit, and for programming a second countvalue in said second counter circuit.
 2. The control circuit as recitedin claim 1 further comprising a clock circuit for generating a singleclock signal to drive both said first and said second counter circuit.3. The control circuit as recited in claim 2 wherein said first countercircuit further comprises a first count detector coupled to a firstcounter.
 4. The control circuit as recited in claim 3 wherein saidsecond counter circuit further comprises a second count detector coupledto a second counter.
 5. The control circuit as recited in claim 4wherein said first count detector and said second count detector arezero count detectors.
 6. The control circuit as recited in claim 3wherein said first counter circuit further comprises a logic circuit,coupled to said first count detector, for providing a BEMF pulse whereinsaid BEMF pulse is said signal on said output line of said first countercircuit that is used to commutate a phase of said spin motor.
 7. Thecontrol circuit as recited in claim 4 wherein said second countercircuit further comprises a second logic circuit, coupled to said secondcount detector, for providing a BEMF pulse wherein said BEMF pulse issaid signal on said output line of said second counter circuit that isused to commutate a phase of said spin motor.
 8. A control circuit asrecited in claim 1 wherein said back EMF output signal is a tachometersignal.
 9. A control circuit for a spin motor having a plurality ofwindings, said control circuit comprising:a back EMF sensing circuitconnectable to at least one winding of said spin motor wherein said backEMF sensing circuit in response to a back EMF induced in said at leastone winding generates a back EMF output signal; a first counter circuithaving an input line coupled to said back EMF sensing circuit and anoutput line coupled to a spin motor sequencer circuit wherein said firstcounter circuit generates a signal on said output line that is used tocommutate a phase of said spin motor; a second counter circuit having aninput line coupled to said back EMF sensing circuit and an output linecoupled to said spin motor sequencer circuit wherein said second countercircuit generates a signal on said output line that is used to commutatesaid phase of said spin motor; a microprocessor interface coupled tosaid first and second counter circuits for programming a first countvalue in said first counter circuit and for programming a second countvalue in said second counter circuit; a start-up circuit including athird counter, and coupled to said spin motor and to said microprocessorinterface wherein said start-up circuit starts said spin motor from astalled condition; and a monitor circuit including a fourth counter, andcoupled to said microprocessor interface and to said spin motor whereinsaid monitor circuit determines the spin direction of said spin motor.10. A startup control circuit for a spin motor comprising:a BEMFgenerating circuit having an input line coupled to said spin motor sothat said input line receives a BEMF signal and an output line whereinsaid BEMF generating circuit generates a BEMF commutation pulse on saidoutput line in response to said BEMF signal on said input line; acounter circuit having an input line, a count direction controlterminal, and an output line; wherein said counter circuit changes acount value in response to a signal on said input line; a startup pulseis generated on said output line upon said count value equaling apredetermined value; and a signal on said count direction controlterminal determines the direction of change of said count value; a logiccircuit having (i) an input line coupled to said output line of saidBEMF generating circuit and (ii) an output line connected to said inputline of said counter circuit; a counter direction control circuit havingan input line connected to said output line of said BEMF generatingcircuit and an output line connected to said count direction controlterminal of said counter circuit;wherein upon startup of said spinmotor, said counter direction control circuit generates a signal havinga first level on said output line so that said count value of saidcounter circuit changes value in a first direction in response to eachclock pulse generated on said output line by said logic circuit; and inresponse to said BEMF commutation pulse, said counter direction controlcircuit generates a signal having a second level to said count directioncontrol terminal of said counter circuit so that said count valuechanges in a second direction different from said first direction. 11.The startup control circuit as recited in claim 10 wherein said countercircuit further comprises:a count value bus wherein said count value buscarries a signal representing said count value; and a count detectorconnected to said count value bus and to said counter circuit outputline wherein said count detector generates said startup pulse upondetection of a selected count value.
 12. The startup control circuit asrecited in claim 10, said counter circuit further comprising:a countvalue bus wherein said count value bus carries a signal representingsaid count value; and a count detector having an input line connected tosaid count value bus and an output line connected to said logiccircuit;wherein said count detector generates a signal on said outputline upon detection of a selected count value; and said logic circuit,in response to a count detector output signal, inhibits generation ofsignals on said output line of said logic circuit.
 13. The startupcontrol circuit as recited in claim 12 further comprising a sequencercircuit having an input line coupled to said counter circuit output linewherein said sequencer circuit commutates a phase of said spin motor inresponse to said startup pulse from said counter circuit.
 14. Thestartup control circuit as recited in claim 13 further comprising afirst pulse generator circuit having (i) an input line connected to theoutput line of said BEMF generating circuit and (ii) an output linecoupled to said sequencer circuit wherein in response to said BEMFcommutation pulse, said first pulse generator circuit generates a pulseon said output line.
 15. The startup control circuit as recited in claim14 wherein said counter direction control circuit comprises a secondpulse generator circuit having (i) an input line connected to the outputline of said BEMF generating circuit and (ii) an output line connectedto said count direction control terminal of said counter circuit whereinsaid input line and said output line of second pulse generator circuitare said input line and output line, respectively, of said counterdirection control circuit.
 16. The startup control circuit as recited inclaim 10 wherein said counter circuit is programmable.
 17. The startupcontrol circuit as recited in claim 16 further comprising amicroprocessor interface coupled to said counter circuit.